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CMX624 v.23/bell 202 modem ? 2001 consumer mi crocircuits limited d/624/6 january 2001 provisional information features applications v.23 / bell 202 compatible modem telephone telemetry systems integrated dtmf encoder remote utility meter reading call progress tone detection security systems/cash terminals line reversal and ring detector industrial contr ol systems low power operation (2.7v) pay - phones part of the cmx6x4 modem series cable tv set - top boxes 1.1 brief description the CMX624 v.23 / bell 202 modem is intended for use in any telephone based information and telemetry system with low power requirements. using fsk signalling, fast call set - up times and robust error resistant transmission can be imple mented by efficient low power circuits. the circuit can operate at 1200bps full duplex over a 4 - wire circuit or 1200 bps plus low speed data over a 2 - wire circuit. flexible line driver and receive hybrid circuitry are integrated on chip requiring only pass ive external components to build a 2 - or 4 - wire interface. a low impedance pull down output is provided for a hook relay. control of the device is via a simple high speed serial bus; this allows easy interfacing to a host controller. the data transmitted and received by the modem is also transferred over the same high speed serial bus. on - chip programmable tx and rx uarts allow asynchronous data to be simultaneously encoded and decoded. either uart may be disabled to allow 8 - bit raw data to be received or transmitted. any repetitive 8 - bit data pattern can be sent without the controller having to reload data every 8 bits. all 16 dtmf combinations are available along with a single tone 'melody' mode. the ringing, 2100hz, call progress and data detectors incl uded on the CMX624 make the set - up of a telephone call a simple matter for the host controller. in many data collection and telemetry systems low power consumption is important. the CMX624 features a 'zero power' standby mode. whilst in standby the ring detector continues to operate and will supply the host controller with an interrupt when line reversal or ringing is detected. the CMX624 can operate on a supply voltage between 3.0v and 5.5v across the full temperature range of - 40c to +85c. the cmx62 4 is pin compatible with the cmx644a v22 and bell 212a modem also from cml.
v23 / bell 202 modem CMX624 ? 2001 consumer microcircuits limited 2 d/624/6 contents section page 1.1 brief description ................................ ................................ ....................... 1 1.2 block diagram ................................ ................................ ........................... 3 1.3 signal list ................................ ................................ ................................ ... 4 1.4 external components ................................ ................................ ............... 6 1.5 general description ................................ ................................ .................. 6 1.5.1 xtal osc and clock dividers ................................ ....................... 6 1.5.2 rx input amplifier ................................ ................................ ........ 7 1.5.3 receive filter and equaliser ................................ ....................... 7 1.5.4 fsk demodulator ................................ ................................ ......... 8 1.5.5 rx energy detector ................................ ................................ ..... 8 1.5.6 fsk / dtmf modulator ................................ ................................ 8 1.5.7 transmit fi lter ................................ ................................ .............. 9 1.5.8 transmit output buffer ................................ ............................. 10 1.5.9 ring signal detector ................................ ................................ .. 10 1.5.10 tx/rx uart ................................ ................................ ................. 11 1.5.11 ?c - bus? interface ................................ ................................ ........ 13 1.5.12 ?c - bus? registers ................................ ................................ ...... 14 1.6 application notes ................................ ................................ .................... 14 1.6.1 line interface ................................ ................................ .............. 15 1.6.2 ring detector interface ................................ ............................. 17 1.7 performanc e specification ................................ ................................ ..... 19 1.7.1 electrical performance ................................ .............................. 19 1.7.2 packaging ................................ ................................ .................... 24 note: this product is in development: changes and additions will be made to this specificati on. items marked tbd or left blank will be included in later issues.
v23 / bell 202 modem CMX624 ? 2001 consumer microcircuits limited 3 d/624/6 1.2 block diagram figure 1 block diagram
v23 / bell 202 modem CMX624 ? 2001 consumer microcircuits limited 4 d/624/6 1.3 signal list CMX624 d2/d5/p4 signal description p in no. name type 1 xtaln o/p the output of the on - chip xtal oscillator inverter. 2 xtal/clock i/p the input to the oscillator inverter from the xtal circuit or external clock source. 3 serial clock i/p the ?c - bus? serial clock input from the m c. see s ection 1.5.11 4 command data i/p the ?c - bus? serial data input from the m c. 5 reply data t/s a 3 - state ?c - bus? serial data output to the m c. this output is high impedance when not sending data to the m c. 6 csn i/p the ?c - bus? transfer control input p rovided by the m c. 7 irqn o/p a ?wire - orable? output for connection to a m c interrupt request input. this output is pulled down to v ss when active and is high impedance when inactive. an external pullup resistor is required. 8 top o/p the tx analogue s ignal output. 9 txo o/p the output of the line driving amplifier. 10 txn i/p the inverting input to the line driver amplifier. 11 txon o/p the inverted output of the line driving amplifier. 12 v ss power the negative supply rail (ground). 13 v bias o/p internally generated bias voltage of v dd /2, except when the device is in ?zero power? mode when v bias will discharge to v ss . should be decoupled to v ss by a capacitor mounted close to the device pins. 14 rlydrv o/p relay drive open drain output. this out put is pulled down to v ss when active and is high impedance when inactive. 15 rxp i/p the non - inverting input to the rx input amplifier.
v23 / bell 202 modem CMX624 ? 2001 consumer microcircuits limited 5 d/624/6 CMX624 d2/d5/p4 signal description pin no. name type 16 rxn i/p the inverting input to the rx input ampli fier. 17 rxo o/p the output of the rx input amplifier. 18 rt bi open drain output and schmitt trigger input forming part of the ring signal detector. 19 rd i/p schmitt trigger input to the ring signal detector. 20 - nc no connection should be made to this pin. 21 - nc no connection should be made to this pin. 22 - nc no connection should be made to this pin if the printed circuit board is to be used for CMX624 only. if the board is also to be used for cmx644a, a capacitor should be connected as sho wn in figure 2. 23 - i/p no connection should be made to this pin if the printed circuit board is to be used for CMX624 only. if the board is also to be used for cmx644a, a capacitor should be connected as shown in figure 2. 24 v dd power the positive supply rail. levels and thresholds within the device are proportional to this voltage. should be decoupled to v ss by a capacitor mounted close to the device pins. notes: i/p = input o/p = output bi = bidirectional t/s = 3 - state output nc = no connection this device is capable of detecting and decoding small amplitude signals. to achieve this v dd and v bias decoupling and protecting the receive path from extraneous in - band signals are very important. it is recommended that the printed circuit b oard is laid out with a ground plane in the CMX624 area to provide a low impedance connection between the v ss pin and the v dd and v bias decoupling capacitors.
v23 / bell 202 modem CMX624 ? 2001 consumer microcircuits limited 6 d/624/6 1.4 external components r1 100k w c1, c2 18pf x1 3.579545mhz c3, c4 0.1 m f c5 * resistors 5%, capacitors 10% unless otherwise stated. * this component is only required for compatibility with cmx644a, see cmx644a data sheet for further details. figure 2 recommended external components for typical application 1.5 general description the CMX624 contains a v.23/bell 202 compatible fsk modem capable of duple x operation at 1200/75 or 1200/150 bps over a 2 - wire line or 1200/1200 bps over a 4 - wire line, a flexible fsk data uart, a receive fsk or call progress tone energy detector, a 2100hz detector, a dtmf generator, a tx line driving buffer amplifier, a telepho ne line ringing signal or line voltage reversal detector and a 3.579545mhz xtal oscillator. these functions are all controlled over a ?c - bus? serial m c interface which also carries the transmit and receive fsk modem data. 1.5.1 xtal osc and clock divider s frequency and timing accuracy of the CMX624 is determined by a 3.579545mhz clock present at the xtal/clock pin. this may be generated by the on - chip oscillator inverter using the external component s c1, c2 and x1 of figure 2, or may be supplied from an external source to the xtal/clock input. if the clock is supplied from an external source, c1, c2 and x1 should not be fitted. the on - chip oscillator is turned off in the 'zero - power' mode. if the clock is provided by an external source which is not always running, then the 'zero - power' mode must be set when the clock is not available. failure to observe this rule may cause a rise in the supply current drawn by CMX624.
v23 / bell 202 modem CMX624 ? 2001 consumer microcircuits limited 7 d/624/6 1.5.2 rx input amplifier this amplifier, with suitable external components, is used to adjust the received signal to the correct amplitude for the fsk receiver and energy detect circuits and may also form part of a 2 - wire or 4 - wire hybri d circuit; see section 1.6.1. 1.5.3 receive filter and equaliser this block includes a bandpass filter whose characteristics are set by bits 4 and 5 of the fsk mode register according to the recei ve operating mode (call progress, 75/150bps fsk or 1200bps fsk). it is used to attenuate out of band noise and interfering signals, especially the locally generated transmit fsk signal which could otherwise interfere with the received fsk signal when the m odem is operating in 2 - wire duplex mode. when receiving 1200bps fsk data an optional equaliser section, enabled by setting bit 6 of the fsk mode register, compensates for one - half of the ets test line 1 characteristics shown in figure 3b. -40 -30 -20 -10 0 100 1000 10000 hz db 1200bps 75/150 bps call progress figure 3a rx fr equency responses with line interface, see section 1.6.1 (equaliser disabled) 0 1 2 3 4 5 0 500 1000 1500 2000 2500 3000 3500 4000 hz db ms db wrt 800hz ms wrt 1700hz figure 3b ets 300 114 test line 1 characteristics (normalised)
v23 / bell 202 modem CMX624 ? 2001 consumer microcircuits limited 8 d/624/6 1.5.4 fsk demodulator this block is enabled when bits 1 and 5 of the fsk mode register are set to ?1?, and converts the 75, 150 or 1200 bps fsk input signal to a binary received data signal which is sent to the rx uart block. note that in the absence of a valid fsk signal, the demodulator may falsely interpret speech o r other extraneous signals as data. 1.5.5 rx energy and 2100hz detector the function of this block is controlled by bits 4 and 5 of the fsk mode register and bit 0 of the tx tones register. when bit 0 of th e tx tones register and bits 4 and 5 of the fsk mode register are set to ?1? this block will measure the frequency and amplitude of the incoming signal. when a signal of 2100hz is present of sufficient amplitude and time bit 4 of the flags register is set high. see section 1.7.1 for amplitude, time and frequency limits. when bit 0 of the tx tones register is set to ?0? this block compares the level of the signal at the output of the receive filter against an internal threshold and may be used as a fsk le vel detector or a simple call progress signal detector according to the settings of bits 4 and 5 of the fsk mode register, which affect the receive filter pass band as described in section 1.5.3. the required register settings are summarised in the table below: tx tones reg fsk mode reg bit 0 bit 5 bit 4 detection mode 0 0 0 call progress 0 1 0 75 / 150 bps fsk 0 1 1 1200 bps fsk 1 1 1 2100 hz bit 4 of the flags register is set to ?1? by the output of this block when the received level has exceede d the threshold for sufficient time. amplitude and time hysteresis are used to reduce chattering in marginal conditions. see section 1.7.1 for definitions of teon and teoff figure 4 rx energy detector timing 1.5.6 fsk / dtmf modulator when bit 7 of the tx tones register is set to ?0? then this block generates fsk signals as determined by bits 0 and 1 of the fsk mode register and the tx data bits from the uart block as shown in the tables below: v.23 mode (bit 7 of setup register = ?0?): fsk mode reg fsk / dtmf modulator block output fsk signal frequency bit 1 bit 0 (bit 7 of tx tones = ?0?) ?0? (space) ?1? (mark) 0 x disabled (o/p held at v dd / 2) - - 1 0 75bps fsk 450hz 390hz 1 1 1200bps fsk 2100 hz 1300hz
v23 / bell 202 modem CMX624 ? 2001 consumer microcircuits limited 9 d/624/6 bell 202 mode (bit 7 of setup register = ?1?): fsk mode reg fsk / dtmf modulator block output fsk signal frequency bit 1 bit 0 (bit 7 of tx tones = ?0?) ?0? (space) ?1? (mark) 0 x disabled (o/p held at v dd / 2) - - 1 0 150bps fsk 487hz 387hz 1 1 1200bps fsk 2200hz 1200hz when bit 7 of the tx tones register is set to ?1?, the block generates dtmf tone pairs or single tones from the dtmf range as shown in the table below. bit 6 of the tx tones register is then used to enable or disable the block?s output to the tx filter. tx data register bits 0 - 3 dtmf tone pairs (tx tones register bit 4 = ?0?) single tone (bit 4 = ?1?) d3 d2 d1 d0 lower frequency (hz) upper frequency (hz) keypad legend single tone frequency (hz) 0 0 0 0 941 1633 d 1633 0 0 0 1 697 1209 1 1209 0 0 1 0 697 1336 2 1336 0 0 1 1 697 1477 3 1477 0 1 0 0 770 1209 4 1209 0 1 0 1 770 1336 5 1336 0 1 1 0 770 1477 6 1477 0 1 1 1 852 1209 7 1209 1 0 0 0 852 1336 8 852 1 0 0 1 852 1477 9 852 1 0 1 0 941 1336 0 941 1 0 1 1 941 1209 * 941 1 1 0 0 941 1477 # 941 1 1 0 1 697 1633 a 697 1 1 1 0 770 1633 b 770 1 1 1 1 852 1633 c 852 1.5.7 transmit filter this stage attenuates out of band signals present at the output of th e fsk/dtmf modulator and also includes a programmable 3db level switch, selected by bit 2 of the fsk mode register. the nominal output levels at the top pin when v dd = 5.0v are as shown below. fsk mode register bit 2 fsk signal dtmf tone (low group) dtmf tone (high group) 0 (low level) - 6db - 5db - 3db 1 (high level) - 3db - 2db 0db 0db = 775mvrms these levels are proportional to v dd , and the actual transmit signal levels present on the 2 - or 4 - wire line will depend on the external circuitry as describe d in section 1.6.1. using the external components recommended in section 1.6.1 for a nominal fsk transmit level of - 9dbm, dtmf tone levels of - 8dbm and - 6dbm, then the out of band energy sent to the line will be within the limits shown in figure 5 for bot h fsk and dtmf signals.
v23 / bell 202 modem CMX624 ? 2001 consumer microcircuits limited 10 d/624/6 -70 -60 -50 -40 -30 -20 -10 0 10 100 1000 10000 100000 hz dbm v23 bell 202 figure 5 maximum out of band tx line energy limits 1.5.8 transmit output buffer this buffer amplifier, connected to the txn, txo and txon pins, is intended for use as a tx line driver as shown in section 1.6.1. two symmetrical outputs are provided for use with a balanced load to give sufficient tx line signal levels even at low v dd . if this is not required the txon output can be disabled. if the buffer is used as a balance d line driver, then bit 6 of the setup register should be set to ?1? (txon output enabled). setting bit 6 to ?0? disables the txon output and the buffer draws less current from the supply. when bit 6 is set to '0' the txon pin should be left open circuit. n.b. the txo output is unaffected by this bit. 1.5.9 ring signal detector this block, which functions even in zero power mode, can be used to detect a telephone line ring signal or line voltage reversal and then generate a interrupt request signal to wake up the c at the start of a call. suitable interface circuits are shown in section 1.6.2. the output of this block is the ?ring detect? line shown in figure 1 which directly drives bit 6 of the flags register. any ?0? to ?1? or ?1? to ?0? change on this line will also set the ?ring detect change? bit (5) of the flags register. if this block is not used, then the rd and rt pins should be connected to v ss and the ?ring detect change? bit (5) of the irq mask register set to ?0?.
v23 / bell 202 modem CMX624 ? 2001 consumer microcircuits limited 11 d/624/6 1.5.10 tx/rx uart this block connects the c, via the ?c - bus? interface, to the received data from the fsk demodulator and to the transmit data input to the fsk modulator. as part of t his function, the block can be programmed to convert data to be transmitted from 7 or 8 - bit bytes to asynchronous data characters, adding start and stop bits and - optionally - a parity bit to the data before passing it to the fsk modulator. similarly, in the receive direction it can extract data bits from asynchronous characters coming from the fsk demodulator, stripping off the start and stop bits and performing an optional parity check on the received data before passing the result over the ?c - bus? to th e c. bits 0 - 3 of the setup register control the number of stop and data bits and the parity options for both receive and transmit directions. data to be transmitted should be loaded by the c into the tx data register when the tx data ready bit (bit 0) o f the flags register goes high. it will then be treated by the tx uart block in one of two ways, depending on the setting of bit 3 of the fsk mode register: if the bit is ?0? (?tx sync? mode) then the 8 bits from the tx data register will be transmitted s equentially at 75, 150 or 1200bps, lsb (d0) first. if bit 3 of the fsk mode register is ?1? (?tx async?) then bits will be transmitted as asynchronous data characters at 75, 150 or 1200 bps according to the following format: one start bit (space). 7 or 8 data bits from the tx data register (d0 - d6 or d0 - d7) as determined by bit 0 of the setup register. lsb (d0) transmitted first. optional parity bit (even or odd parity) as determined by bits 1 and 2 of the setup register. one or two stop bits (mark) as determined by bit 3 of the setup register. in both cases data will only be transmitted if bit 1 of the fsk mode register is set to ?1?. failure to load the tx data register with a new value when required will result in bit 1 (tx data underflow) of the flags register being set to ?1? and if the ?tx async? mode of operation had been selected then a continuous mark (?1?) signal will then be transmitted until a new value is loaded into tx data, whereas in ?tx sync? mode the byte already in the tx data regis ter will be re - transmitted. figure 6a transmit uart function (async)
v23 / bell 202 modem CMX624 ? 2001 consumer microcircuits limited 12 d/624/6 received data from the fsk demodulator goes into the receive part of the uart block, where it is handled in one of two ways depending on the setting of bit 7 of the fsk mode regis ter: if the bit is ?0? (?rx sync? mode) then the receive part of the uart block will simply take 8 consecutive bits from the demodulator and transfer them to the rx data register (the first bit going into the d0 position). note that this mode is intended for detection of simple data patterns such as ?1010?? or continuous mark or space signals, the CMX624?s receive data clock extraction circuits are not adequate to support a true synchronous receive data mode of operation. if bit 7 of the fsk mode registe r is ?1? (? rx async?) then the received data output of the fsk demodulator is treated as 75, 150 or 1200 bps asynchronous characters each comprising: a start bit (space). 7 or 8 data bits as determined by bit 0 of the setup register. these bits will be placed into the rx data register with the first bit received going into the d0 position. an optional parity bit as determined by bits 1 and 2 of the setup register. if parity is enabled (bit 2 of the setup register = ?1?) then bit 7 of the flags register will be set to ?1? if the received parity is incorrect. at least one stop bit (mark). bit 2 (rx data ready) of the flags register will be set to ?1? every time a new received value is loaded into the rx data register. if the previous contents of the rx d ata register had not been read out over the ?c - bus? before the new value is loaded from the uart then bit 3 (rx data overflow) of the flags register will also be set to ?1?. figure 6b receive uart function (async)
v23 / bell 202 modem CMX624 ? 2001 consumer microcircuits limited 13 d/624/6 1.5.11 ?c - bus? interface this block provides for the transfer of data and control or status information between the CMX624?s internal registers and the c over the ?c - bus? serial bus. each transaction, see figure 7, consists of a single regist er address byte sent from the c which may be followed by a single data byte sent from the c to be written into one of the CMX624?s write only registers, or a single byte of data read out from one of the CMX624?s read only registers, as illustrated in fig ure 7. data sent from the c on the command data line is clocked into the CMX624 on the rising edge of the serial clock input. reply data sent from the CMX624 to the c is valid when the serial clock is high. the interface is compatible with the most comm on c serial interfaces such as sci, spi and microwire, and may also be easily implemented with general purpose c i/o pins controlled by a simple software routine. see figure 10 for detailed ?c - bus? timing requirements. figure 7 ?c - bus? transactions
v23 / bell 202 modem CMX624 ? 2001 consumer microcircuits limited 14 d/624/6 1.5.12 ?c - bus? registers write only ?c - bus? registers command data byte bits addr reg. 7 6 5 4 3 2 1 0 $01 reset n/a n/a n/a n/a n/a n/a n/a n/a $e0 setup fsk mode: 0 = v.23 1 = bell 202 txon o/p: 0 = off 1 = on relay drive: 0 = o/c 1 = pull low 0 = zero power 1 = normal stop bits: 0 = 1 bit 1 = 2 bits parity: 0 = none 1 = parity parity: 0 = odd 1 = even data bits: 0 = 8 bits 1 = 7 bits $e1 tx tones tx mode: 0 = fsk. 1 = tones. tone or fsk o/p: 0 = off. 1 = on. reserved, set to 0 0 = dtmf 1 = single tone reserved, set to 0 reserved, set to 0 reserved, set to 0 set detect: 0 = fsk/cp 1 = 2100hz $e3 tx data d7 d6 d5 d4 d3 d2 d1 d0 $e7 fsk mode 0 = rx sync 1 = async rx equal: 0 = off 1 = on 0 = rx call progress 1 = rx fsk 0 = rx 75 / 150 bps 1 = 1200 0 = tx sync 1 = async tx o/p level: 0 = normal 1 = +3db fsk enable: 0 = off 1 = on (tx & rx) 0 = tx 75 / 150 bps 1 = 1200 or dtmf $ee irq mask reserved, set to 0 reserved, set to 0 ring detec t change reserved, set to 0 rx data overflow rx data ready tx data underflow tx data ready read only ?c - bus? registers reply data byte bits addr reg. 7 6 5 4 3 2 1 0 $ea rx data d7 d6 d5 d4 d3 d2 d1 d0 $ef flags bad rx parity ring detect ring detect change ** rx energy or 2100hz detect. rx data overflow ** rx data ready ** tx data underflow ** tx data ready ** ** see notes 2 and 3 notes: 1. accessing the reset register over the ?c - bus? clears all of the bits in the setup, tx tones, tx dat a, fsk mode and irq mask registers, and bits 0 - 3 and 5 of the flags register to ?0?. this will set the device into zero power mode. note that this is a single - byte ?c - bus? transaction consisting solely of the address byte value $01. note that putting th e device in zero power mode by directly setting setup bit 4 to ?0? does not clear the other register bits. care should be taken before re - enabling the device that the other bits are set so as to prevent undesired transient operation. in particular, bit 6 of the txtones register should be set to ?0? to prevent modulation of the transmitter output. 2. if any of bits 0, 1, 2, 3 or 5 of the flags register is ?1? and the corresponding bit of the irq mask register is also ?1? then the irqn output of the CMX624 wi ll be pulled low. 3. bit 5 (ring detect change) of the flags register is set on every ?0? to ?1? or ?1? to ?0? change of bit 6 (ring detect). 4. clearing bit 4 of the setup register puts the CMX624 into the zero power mode by turning off all blocks except for the ?c - bus? interface and ring detector circuit. 5. reading the flags register clears the irqn output and also clears bits 0, 1, 2, 3 and 5 of the flags register. 6. flags register (bit 4) is ?1? whenever the received signal being looked for is detected and ? 0? when both signals are absent. irq mask register (bit 4) is normally set to ?0? - but can be set to ?1? to enable interrupts on the irqn output. in the latter case, irqn will be continuously pulled to ?0? whilst rx energy or 2100hz are present. this m ay be useful for device evaluation purposes. 1.6 application notes
v23 / bell 202 modem CMX624 ? 2001 consumer microcircuits limited 15 d/624/6 1.6.1 line interface a line interface circuit is needed to provide dc isolation between the modem and the line, to perform line impedance termination, and to set the correct transmit and receive signal levels. 4 - wire line interface figure 8a shows an interface circuit for use with a 600 w 4 - wire line. the line terminations are provid ed by r10 and r15, while r11 and r13 should be selected to give the desired transmit and receive levels. the gain of the receive input amplifier (r12 / r11) should be set to compensate for the loss of the input transformer and the supply voltage. assumi ng transformer loss of about 1db, r11 should be 91k w at 5.0v, or 130k w at 3.0v. note relay circuit, ac and dc loads and line protection not shown for clarity. r10 600 w r13 see text c10 100nf r11 see text r14 100k w c11 220pf r12 100k w r15 600 w c12 330pf c13 100nf resistors 1%, capacitors 20%. figure 8a 4 - wire line interface circuit
v23 / bell 202 modem CMX624 ? 2001 consumer microcircuits limited 16 d/624/6 in the transmit direct ion, the level on the 4 - wire line is determined by the level at the top pin, the gain of the output buffer amplifier, a loss of nominally 6db due to the line termination resistor r15, and the loss in the transformer. the top pin signal level is proportio nal to v dd and is also affected by the setting of the tx o/p level control bit (bit 2) of the fsk mode register. assuming that the tx o/p level control bit is set to ?1? (giving a fsk signal level of - 3db wrt 775mvrms at the top pin when v dd = 5.0v) and that there is 1db loss in the transformer, then: tx fsk 4 - wire line level = - (3 +6 +1) + 20 x log 10 (2 x r14 / r13) + 20 x log 10 (v dd / 5.0) dbm for example, to generate a nominal tx fsk line level of - 9dbm, r13 should be 180k w w hen v dd = 5.0v, falling to 120k w at 3.3v. 2 - wire line interface figure 8b shows an interface circuit suitable for connection to a 600 w 2 - wire line. the circuit also shows how a relay may be driven from the rlydrv pin. note that when the CMX624 is powered from less than 5.0v, buffer circuitry will be required to drive a 5v relay. note ac and dc loads and line protection not shown for clarity. r11 see text r15 600 w c11 220pf r12 100k w r16 120k w c12 330pf r13 see text r17 100k w c13 10nf r14 100k w c14 100nf resistors 1%, capacitors 20% figure 8b 2 - wire line interface c ircuit this circuit includes a 2 - wire to 4 - wire hybrid circuit, formed by r11, r15, r16, r17, c13 and the impedance of the line itself, which ensures that the modem receive input and transmit output paths are both coupled efficiently to the line, while mi nimising coupling from the modem?s transmit signal into the receive input. the values of r11 and r13 should be calculated in the same way as for the 4 - wire interface circuit of figure 8a.
v23 / bell 202 modem CMX624 ? 2001 consumer microcircuits limited 17 d/624/6 1.6.2 ring detector interface figure 9 shows how the CMX624 may be used to detect the large amplitude ringing signal received at the start of an incoming telephone call. the ring signal is usually applied at the subscriber's exchange as an ac voltage inserted in serie s with one of the telephone wires and will pass through either c20 and r20 or c21 and r21 to appear at the top end of r22 (point x in figure 9) in a rectified and attenuated form. the signal at point x is further attenuated by the potential divider form ed by r22 and r23 before being applied to the CMX624 rd input. if the amplitude of the signal appearing at rd is greater than the input threshold (vthi) of schmitt trigger 'a' then the n transistor connected to rt will be turned on, pulling the voltage at rt to v ss by discharging the external capacitor c22. the output of the schmitt trigger 'b' will then go high, setting bit 6 (ring detect) of the flags register. the minimum amplitude ringing signal that is certain to be detected is: ( 0.7 + vthi x [r20 + r22 + r23] / r23 ) x 0.707 vrms where vthi is the high - going threshold voltage of the schmitt trigger a (see section 1.7.1). with r20 - 22 all 470k w as figure 9, then setting r23 to 68k w will guarantee detec tion of ringing signals of 40vrms and above for v dd over the range 3.0 to 5.5v. r20, 21, 22 470k w c20, 21 0.1 m f r23 see text c22 0.33 m f r24 470k w d1 - 4 1n4004 resistors 1%, capaci tors 20% figure 9 ring signal detector interface circuit
v23 / bell 202 modem CMX624 ? 2001 consumer microcircuits limited 18 d/624/6 if the time constant of r24 and c22 is large enough then the voltage on rt will remain below the threshold of the 'b' schmitt trigger for the duration of a ring cycle. the time for the voltage on rt to charge from v ss towards v dd can be derived from the formula v rt = v dd x [1 - exp( - t/(r24 x c22)) ] as the schmitt trigger high - going input threshold voltage (vthi) has a minimum value of 0.56 x v dd , then the schmitt trigge r b output will remain high for a time of at least 0.821 x r24 x c22 following a pulse at rd. the values of r24 and c22 given in figure 9 (470k w and 0.33 m f) give a minimum rt charge time of 100 msec, which is adequate for ring frequencies of 10hz or above. note that the circuit will also respond to a telephone line voltage reversal. if necessary the m c can distinguish between a ring signal and a line voltage reversal by measuring the time that bit 6 of the f lags register (ring detect) is high.
v23 / bell 202 modem CMX624 ? 2001 consumer microcircuits limited 19 d/624/6 1.7 performance specification 1.7.1 electrical performance 1.7.1.1 absolute maximum ratings exceeding these maximu m ratings can result in damage to the device. min. max. unit supply (v dd - v ss ) - 0.3 7.0 v voltage on any pin to v ss - 0.3 v dd + 0.3 v current into or out of v dd and v ss pins - 50 +50 ma current into rlydrv pin +50 ma current into or out o f any other pin - 20 +20 ma d2 package min. max. unit total allowable power dissipation at tamb = 25c 800 mw ... derating 13 mw/c storage temperature - 55 +125 c operating temperature - 40 +85 c d5 package min. max. unit total a llowable power dissipation at tamb = 25c 550 mw ... derating 9 mw/c storage temperature - 55 +125 c operating temperature - 40 +85 c p4 package min. max. unit total allowable power dissipation at tamb = 25c 800 mw ... derating 13 mw/c storage temperature - 55 +125 c operating temperature - 40 +85 c 1.7.1.2 operating limits correct operation of the device outside these limits is not implied. notes min. max. unit supply (v dd - v ss ) 2.7 5.5 v operating temper ature - 40 +85 c xtal frequency 1 3.575965 3.583125 mhz notes: 1. a xtal frequency of 3.579545mhz 0.1% is required for correct operation.
v23 / bell 202 modem CMX624 ? 2001 consumer microcircuits limited 20 d/624/6 1.7.1.3 operating characteristics details in this section represent design target values and are not currently guaranteed. for the following conditions unless otherwise specified: v dd = 2.7v at tamb = 25c and v dd = 3.0v to 5.5v at tamb = - 40 to +85c, xtal frequency = 3.579545mhz 0.1%, 0dbm corresponds to 775mvrms. dc param eters notes min. typ. max. unit i dd (zero power mode) 1, 2 - 1.0 - m a (running, txon o/p off, v dd = 5.0v) 1 - 3.4 6.0 ma (running, txon o/p off, v dd = 3.3v) 1 - 1.8 3.2 ma (running, txon o/p on, v dd = 5.0v) 1 - 3.5 6.2 ma (running, txon o/p on, v dd = 3.3v) 1 - 1.9 3.4 ma logic '1' input level 3 70% - - v dd logic '0' input level 3 - - 30% v dd logic input leakage current (vin = 0 to v dd ), (excluding xtal/clock input) - 1.0 - +1.0 m a output logic '1' level (l oh = 360 m a) v dd - 0.4 - - v output logic '0' level (l ol = 360 m a) - - 0.4 v irqn o/p 'off' state current (vout = v dd ) - - 1.0 m a sc hmitt trigger input high - going threshold (vthi) (see figure 11) 0.56v dd - 0.56v dd + 0.6v v schmitt trigger input low - going threshold (vtlo) (see figure 11) 0.44v dd - 0.6v - 0.44v dd v rlydrv ?on? resistance to v ss (v dd = 5.0v) - 38.0 tbd w notes: 1. at 25 c, not including any current drawn from the CMX624 pins by external circuitry other than x1, c1 and c2. 2. all logic inputs at v ss except for rt and csn inputs which are at v dd . 3. excluding rd, rt and xtal/clock pins. fsk modulator and tx uart notes min. typ. max. unit level at top pin. 4 - 4.0 - 3.0 - 2.0 dbm twist (mark level wrt space level) - 2.0 0 +2.0 db tx 1200bits/sec (v.23 mode) baud rate (set by uart and xtal freque ncy) 1194 1200 1206 baud mark (logical 1) frequency 1297 1300 1303 hz space (logical 0) frequency 2097 2100 2103 hz tx 75bits/sec (v.23 mode) baud rate (set by uart and xtal frequency) 74 75 76 baud mark (logical 1) frequenc y 388 390 392 hz space (logical 0) frequency 448 450 452 hz tx 1200bits/sec (bell 202 mode) baud rate (set by uart and xtal frequency) 1194 1200 1206 baud mark (logical 1) frequency 1197 1200 1203 hz space (logical 0) freque ncy 2197 2200 2203 hz tx 150bits/sec (bell 202 mode) baud rate (set by uart and xtal frequency) 149 150 151 baud mark (logical 1) frequency 385 387 389 hz space (logical 0) frequency 485 487 489 hz notes: 4. at v dd = 5.0v, tx o /p level control bit set to ?1?; load resistance greater than 40k w .
v23 / bell 202 modem CMX624 ? 2001 consumer microcircuits limited 21 d/624/6 dtmf transmitter notes min. typ. max. unit level at top pin; tones in high group 4 - 1.0 0.0 +1.0 dbm twist (level of high group tones wrt level of low gro up tones) - +2.0 - db tone frequency accuracy (worst case) - 0.5 - +0.5 % tx filter and output buffer notes min. typ. max. unit change in level at top pin caused by changing bit 2 of fsk mode register 2.5 3.0 3.5 db buffer output signal swing; load greater than 500 w . 5 2.2 - - vp - p notes: 5. for each of the txon (if enabled) and txo pins, load between pin and v dd / 2. fsk demodulator and rx uart notes min. typ. max. unit valid input level range 6 - 43.0 - - 9.0 dbm acceptable twist (mark level wrt space level) - 7.0 - +7.0 db acceptable signal to noise ratio 7 20.0 - - db rx 1200bits/sec (v.23 mode) acceptable rx data rate 8 1188 1200 1212 baud mark (logical 1) frequency 1280 1300 13 20 hz space (logical 0) frequency 2068 2100 2132 hz rx 75bits/sec (v.23 mode) acceptable rx data rate 8 tbd 75 tbd baud mark (logical 1) frequency tbd 390 tbd hz space (logical 0) frequency tbd 450 tbd hz rx 1200bits/sec ( bell 202 mode) acceptable rx data rate 8 1188 1200 1212 baud mark (logical 1) frequency 1180 1200 1220 hz space (logical 0) frequency 2168 2200 2232 hz rx 150bits/sec (bell 202 mode) acceptable rx data rate 8 tbd 150 tbd baud mark (logical 1) frequency tbd 387 tbd hz space (logical 0) frequency tbd 487 tbd hz notes: 6. measured at point a in figures 8a and 8b, for v dd = 5.0v. the internal threshold levels are proportional to v dd . to cater for other supply v oltages or different signal level ranges the voltage gain of the rx input amplifier should be adjusted by selecting the appropriate external components as described in section 1.6.1. 7. flat noise in 300 - 3400 hz band for v.23 , 200 - 3400 hz for bell 202. 8. set by rx uart and xtal frequency. 2100hz detector notes min. typ. max. unit ?will decode? frequency range 2040 - 2235 hz ?will not decode? frequency range <2010 - >2265 hz ?off? to ?on? time 9 - - 25 ms ?on? to ?off? time 9 4.0 - - ms note s: 9. 2100hz detection requires a signal within the amplitude range given in the rx energy detector section.
v23 / bell 202 modem CMX624 ? 2001 consumer microcircuits limited 22 d/624/6 rx energy detector notes min. typ. max. unit ?off? to 'on' threshold level (fsk) 6, 10 - 48.0 - - 43.0 dbm ?off? to 'on' threshold level (call progress) 6, 10 - 48.0 - - 40.0 dbm hysteresis (measured at v dd = 3v and 5v) 6, 10 2.0 - - db 'off' to 'on' time (figure 4 teon): 6, 10 1200bps rx mode - - 25 ms 75/150bps rx mode - - 48 ms call progress detect mode - - 48 ms 'on' to 'off' time (figure 4 teoff): 6, 10 1200bps rx mode 8.0 - - ms 75/150bps rx mode 20 - - ms call progress detect mode 20 - - ms notes: 10. measured with 1300hz signal in 1200bps mode, 390hz for 75 or 150 b ps and call progress mode, signal level - 33dbm for time delay measurements. xtal/clock input notes min. typ. max. unit 'high' pulse width 11 100 - - ns 'low' pulse width 11 100 - - ns notes: 11. timing for an external input to the xtal/clock pin. ?c - bus? timings (see figure 10) notes min. typ. max. unit t cse csn - enable to clock - high time 100 - - ns t csh last clock - high to csn - high time 100 - - ns t loz clock - low to reply output enable time 0.0 - - ns t hiz csn - high to reply out put 3 - state time - - 1.0 s t csoff csn - high time between transactions 1.0 - - s t nxt inter - byte time 200 - - ns t ck clock - cycle time 200 - - ns t ch serial clock - high time 100 - - ns t cl serial clock - low time 100 - - ns t cds command data set - up time 75 - - ns t cdh command data hold time 25 - - ns t rds reply data set - up time 50 - - ns t rdh reply data hold time 0 - - ns note: these timings are for the latest version of the ?c - bus? as embodied in the CMX624, and allow faster transfers than the original ?c - bus? timings given in cml publication d/800/sys/3 july 1994.
v23 / bell 202 modem CMX624 ? 2001 consumer microcircuits limited 23 d/624/6 figure 10 ?c - bus? timing 0 0.5 1 1.5 2 2.5 3 3.5 2.5 3 3.5 4 4.5 5 5.5 vdd vin vthi vtlo figure 11 typical schmitt trigger input voltage thresholds vs. v dd
v23 / bell 202 modem CMX624 ? 2001 consumer microcircuits limited 24 d/624/6 1.7.2 packaging figure 12a 24 - pin soic (d2) mechanical outline: order as part no. CMX624d2 figure 12b 24 - pin ssop (d5) mechanical outline: order as part no. CMX624d5
v23 / bell 202 modem CMX624 handling precautions: this product includes input protection, however, p recautions should be taken to prevent device damage from electro - static discharge. cml does not assume any responsibility for the use of any circuitry described. no ipr or circuit patent licences are implied. cml reserves the right at any time without n otice to change the said circuitry and this product specification. cml has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. specific testing of all circuit parameters is not n ecessarily performed. oval park - langford maldon - essex cm9 6wg - england telephone: +44 (0)1621 875500 telefax: +44 (0)1621 875600 e - mail: sales@cmlmicro.co.uk http://www.cmlmicro.co.uk figure 12c 24 - pin dil (p4) mechanical outline: order as part no. cmx6 24p4

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